1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device incorporating a flash memory circuit fabricated by a Complementary Metal Oxide Silicon fabrication process (CMOS fabrication process).
2. Description of the Prior Art
Over the past years, semiconductor integrated circuits fabricated by using the CMOS fabrication process are widely and commonly used as memories because they have the advantage of a higher integration. Recently, it is proposed and widely used to fabricate both a semiconductor integrated circuit and a flash memory circuit on a same semiconductor chip by using the CMOS fabrication process in order to increase the integration.
FIG. 10 is a block diagram showing a configuration of a conventional semiconductor integrated circuit device fabricated by the concept described above. In FIG. 10, the reference number 1 designates a central processing unit (CPU) incorporated in the semiconductor integrated circuit device, 2 denotes a flash memory circuit incorporated in the semiconductor integrated circuit device, and 3 indicates an I/O port incorporated in the semiconductor integrated circuit device. The reference number 4 designates a bus having a plurality of lines through which the CPU 1, the flash memory circuit 2, the I/O port 3, and the like are electrically connected. The reference number 5 designates each of input terminals of the semiconductor integrated circuit device, and 6 denotes each of output terminals of the semiconductor integrated circuit device. The reference number 7 indicates each of input buffers. Each input buffer 7 is located between each input terminal 5 and the I/O port 3 and provides an input signal (that is received through each input terminal 5) to each sections in the semiconductor integrated circuit device such as the CPU 1, the flash memory circuit 2, and the like. The reference number 8 indicates each of output buffers. Each output buffer 8 is located between each output terminal 6 and the I/O port 3 and drives each corresponding output terminal 6.
Next, a description will be given of one example of the operation of the conventional semiconductor integrated circuit device shown in FIG. 10.
In the conventional semiconductor integrated circuit device, when a reset signal that is inputted into the input terminal 5 to be used for resetting operation is canceled or released, the CPU 1 initiates its operation. In one concrete example, the CPU 1 initiates to perform a sequential operation based on data that have been stored in the flash memory circuit 2. Hereinafter, it is referred to as a normal operation mode.
When the semiconductor integrated circuit device described above operates during the boot operation mode in which data items are written into the flash memory circuit 2, the reset signal is canceled or released under the state in which a boot mode control signal has been inputted into the input terminal 5. Thereby, the CPU 1 judges that the mode when the reset signal is canceled or released is the start up of or the rising state of the boot mode based on the voltage level of the input terminal 5 indicating the boot mode. Then, the CPU 1 writes data items that have been provided to the data input terminal 5 into the flash memory circuit 2, sequentially. This writing operation by the CPU 1 sets various data items to be used for applications of the semiconductor integrated circuit device.
When the normal mode is risen after this boot mode, the CPU 1 reads the data items stored in the flash memory circuit 2 sequentially and executes them as initial setting operations and the like.
In order to switch the operation of the CPU 1 during the releasing operation of the reset signal, for example, a boot program to be used for executing the boot mode has been stored in a read only memory (ROM) incorporated in the semiconductor integrated circuit device. Thereby, the operation flow jumps to a starting address of the boot program according to the mode when the reset signal is canceled or released, for example.
As described above, it is possible to obtain the semiconductor integrated circuit device, in which both the central processing unit 1 and the flash memory circuit 2 are mounted on the same semiconductor chip, that is capable of applying higher versatile uses easily.
However, when the above conventional semiconductor integrated circuit device incorporating the flash memory circuit and the CPU on the same semiconductor chip fabricated by using the CMOS fabrication process is used, there causes a drawback in which the magnitude of a current flow during the boot operation mode becomes greater than that of a current flow in the normal operation mode. The increasing of the magnitude of the current flow causes to reduce the life time of the semiconductor integrated circuit device and also to decrease the reliability of the semiconductor integrated circuit device.
In order to avoid the drawback in the conventional semiconductor integrated circuit device described above, the inventors of the present invention researched and studied this conventional drawback and found the cause thereof. That is, the increasing of the current flow during the boot operation mode is caused under the state in which the voltage potential of each of the input terminals that are not used for the boot operation mode enters a floating state and input terminals of the internal devices connected to those input terminals have an immediate voltage potential that is not the high voltage level and not the low voltage level. As a result, both P channel MOS transistor and N channel MOS transistor forming each of the internal devices such as the input buffers enter the ON state. This ON state causes to flow a penetrate current through the internal circuits such as the input buffers and to increase the magnitude of the current flow during the boot operation mode. This also causes to increase the power consumption of the conventional semiconductor integrated circuit device. The inventors have solved this conventional drawback and invents the present invention.